Research Topic
Hardware-software co-design for FPGA-based deep learning acceleration, AI compiler frameworks, and sparsity-aware NPU architectures.
Supervisor
- Professor Christian Plessl (Paderborn Center for Parallel Computing)
Thesis Abstract
This thesis pursues two parallel thrusts in hardware-software co-design for FPGA-based AI acceleration. The first matures an AI compiler framework toward production-grade reliability and broader model support, extending operator coverage across convolutional, transformer, and post-transformer architectures. The second designs a sparsity-aware mesh-of-tiles Neural Processing Unit in VHDL, prototyped on the OTUS FPGA cluster and validated to Post-PnR. Both converge in a unified benchmark comparing compiler-generated dataflow, hand-coded RTL, the custom NPU, and commercial NPUs.
Publications
- Bruno M. S. Teixeira et al. “Understanding Signal Feature Impact in CNN-Based Modulation Classification with Realistic Datasets”. In: Computational Science and Its Applications – ICCSA 2025 Workshops: Istanbul, Turkey, June 30 – July 3, 2025, Proceedings, Part I. Istanbul, Türkiye: Springer-Verlag, 2025, pp. 124–136.
- Thalles M. Moreira, Fábio D. L. Coutinho, and Arnaldo S. R. Oliveira. “AI Frameworks and DL Processing Units Performance Evaluation for CNN-Based Real-Time RF Modulation Classification”. In: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. HEART ’25. ACM. Kumamoto, Japan: ACM Press, 2025, pp. 147–155
Conference Presentations
- HEART 2025, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Kumamoto, Japan, May 2025