Research Topic
Making large-scale low-level hardware design more feasible.
A new RTL language for the design of high-performance FPGA accelerators
Supervisors
Professor Christian Plessl (NHR@PC2)
Thesis abstract
SUS: A language for building deeply pipelined, high frequency FPGA accelerators.
During my doctorate, I developed a language 'SUS', which encodes the pipeline depth of logic in the type system. This lets one design hardware containing complex pipelining arrangements with little mental overhead. In the last year of the thesis, I apply the language to real hardware designs, such as 'SUSpMV', in which we thoroughly surpassed the SOTA on the problem of Sparse Matrix Vector Multiplication. Further accelerators will still follow this year.
Secondment
NHR4CES@TUDa
Publications
- [FPT26] SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS
Conference Presentations
- Latency Counting in the SUS Language [LATTE24] https://www.youtube.com/watch?v=7P0BvXSHLpY
- SUS: A new language for efficient Hardware Design [deRSE25]